Please use this identifier to cite or link to this item: http://repo.lib.jfn.ac.lk/ujrr/handle/123456789/507
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dc.contributor.authorTharaka, R.M.R.
dc.contributor.authorBandara, R.W.K.M.R.K.D.
dc.contributor.authorAbeyratna, S.G.
dc.contributor.authorAtputharajah, A.
dc.contributor.authorFernando, M.A.R.M.
dc.contributor.authorNavarathne, D.N.
dc.date.accessioned2014-07-07T08:09:11Z
dc.date.accessioned2022-06-27T10:02:13Z-
dc.date.available2014-07-07T08:09:11Z
dc.date.available2022-06-27T10:02:13Z-
dc.date.issued2013-12
dc.identifier.urihttp://repo.lib.jfn.ac.lk/ujrr/handle/123456789/507-
dc.description.abstractA new configuration to replace the Thyristor Controlled Reactor (TCR) of a Static VAR Compensator (SVC) by a DC link voltage controlled inductor is proposed in this paper. In this proposed technique, the reactor current contribution is regulated by controlling the peak current through the reactor which conducts for a complete cycle. This is in-contrast with delaying the firing angle to limit the conducting window in the conventional method. The proposed technique remedies the deformation on current waveform at the peak of the injected current, by transferring the waveform deformation to the zero crossing. This results a fairly good waveform which is very much closer to the fundamental sinusoidal, hence harmonic distortion is reduced. The new technique shows better harmonic performance for the upper side of the capacitor step. For de-rated capacitor steps, harmonic performance of the new technique is better than the conventional arrangement as well, enabling dynamic capacitor bank sizing for varying load patterns. Conventional and proposed methods are simulated using EMTDC/PSCAD software package and results are presented and compared in this paper.en_US
dc.language.isoenen_US
dc.publisherIEEE 8th International Conference on Industrial and Information Systemsen_US
dc.titleA Novel Concept for Static VAR Compensatorsen_US
dc.typeArticleen_US
Appears in Collections:Electrical & Electronic Engineering

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